The Assembly Hall of Shame: hunting x86's single slowest instructions

Most instruction-latency work chases speed. Chris Domas’s Assembly Hall of Shame (published under his xoreaxeaxeax handle) runs the experiment backward, crowning whichever single x86 instruction can be coerced into taking the longest. The rules are strict: only one instruction is scored, it cannot be interruptible, trapped-and-emulated instructions may only count the trap itself, and every machine runs in factory-stock configuration with times normalized to base clock. Baselines start where you’d expect—a plain nop clocks 1 cycle, rdtsc around 49—but the leaderboard quickly leaves the microarchitecture behind.

The winning tricks are a tour of how modern CPUs actually fail to be fast. Denormal and special-value operands (fldl, fsin, fadd, fdiv) kick the FPU into slow microcode assists; split-lock operands straddling a cache line force the external bus lock; wbinvd flushes the entire dirty cache hierarchy to DRAM; rdrand is run in a tight loop to drain the hardware entropy pool until it stalls; and obscure or undocumented MSRs (a VIA register at 0x133, AMD’s MCG_CTL) push single reads and writes into the hundreds of thousands of cycles. The real blowups come from stepping off the die entirely: mov and in/out instructions aimed at high-latency MMIO deadspace and I/O ports in the PCIe fabric turn one instruction into millions of cycles. The top entry uses fxrstor64 to load 512 bytes of FPU state from a slow MMIO region while a fleet of ‘hammer’ cores saturates the PCIe root complex with non-posted transactions—stretching a single instruction on an AMD Ryzen 7 5800H to roughly 198 billion cycles, or 62 seconds.

Beyond the sport, several entries carry a security edge. One writeup describes using a spec-violating unaligned ymm0 load to generate non-posted transactions from stalled GPU registers and break System Management Mode—a reminder that the same fabric-level stalls that win this contest are the kind of timing and coherence quirks that undermine hardware trust boundaries. It’s a playful leaderboard, but it doubles as a catalog of where CPU determinism quietly breaks down.