RISCBoy: an open-source handheld console built from a custom RISC-V chip up

RISCBoy is a from-scratch, open-source portable games console — effectively a Game Boy Advance reimagined as if RISC-V had existed in 2001. The project spans the full stack: a RISC-V compatible soft CPU, a raster graphics pipeline and display controller, supporting chip infrastructure (bus fabric, memory controllers, UART, GPIO), and a KiCad PCB layout. Everything is written in synthesisable Verilog 2005 and targets a modest Lattice iCE40-HX8k FPGA with only 7,680 logic elements, so squeezing a 32-bit console onto it demands careful design rather than brute force.

The processor core, named hazard5, implements the RV32IMC instruction set and is verified against the official RISC-V compliance suite, the riscv-formal framework, and the author’s own formal property checks for frontend consistency and bus compliance. It also supports M-mode CSRs, exceptions, and a lightweight vectored interrupt extension. Smaller boards like the iCE40 UP5k can run a cut-down RV32I variant, though the docs warn sharply that linking RV32I code against RV32IMC libraries will break things. The build flow leans entirely on open toolchains — Yosys, nextpnr, and Project Icestorm for the iCE40 target, with experimental ECP5 support via Trellis — while simulation still uses Xilinx ISIM.

The significance here is less about a shippable product and more about what a single-person, fully open hardware/software project can now achieve. RISCBoy demonstrates a complete embedded system — silicon design, graphics, peripherals, and PCB — assembled with free FPGA tooling and an open ISA. The author frames it candidly as a hobbyist labor of love (“a 3AM drunk text to the technology”) rather than a polished platform: the software tree is thin, Rev B hardware is on hold pending gateware maturity, and the toolchain has since moved past the once-flagship HX8k. Still, it’s a compelling reference for anyone learning CPU design, RISC-V verification, or open-source FPGA workflows.