RISC-V's ISA Sins: Slow Interrupts and Broken Compressed Encoding

A longtime RISC-V critic lays out a technical case that the architecture’s much-praised ISA is mediocre where it matters most. The central argument is that no single instruction set can be optimal from supercomputers down to disposable microcontrollers — the demands are genuinely opposed at the architecture level, not just the microarchitecture. The author concedes RISC-V will eventually dominate cheap, single-purpose microcontrollers, but only by beating the ancient 8051, a bar he calls a speed bump, rather than by being well designed.

The sharpest complaint is interrupt handling. Because the base ISA has no hardware register stacking, a spec-compliant handler must manually save and restore the ABI registers, costing roughly 44 cycles of overhead before any real work — 38 even with the reduced-register RV32E — versus 27 cycles on ARM’s decade-old Cortex-M0, which pushes registers in hardware and lets handlers be written directly in C. That gap has pushed vendors to bolt on non-standard fast-interrupt extensions like CLIC just to reach parity, which the author reads as an indictment that further fragments the ‘standard.’

He is equally scornful of the compressed (C) instruction set that RISC-V advocates tout for code density. The 16-bit store-byte instruction encodes offsets of only 0–3 and store-halfword only 0–2, with an addressing bit needlessly wired to zero, against Cortex-M0’s ranges of 0–31, 0–62 and 0–124. Worse, those byte and halfword stores live in a separate Zcb extension that may not even be present. The recurring theme is extension sprawl: optional pieces that undermine any coherent notion of a portable baseline.