One bit-flip in AMD's DRAM controller unlocks PSP, SMM, and microcode

The tool skitter-creek-bath-salts attacks the lowest, least-examined layer of the memory pipeline: the AMD memory controller (MCT/DCT), where a physical address gets its final translation into raw DRAM coordinates — bank group, bank, row, and column. By poking configuration bits in that controller, such as the DCT bank-swizzle mode, an attacker rewires the mapping on a live system. A physical address stops landing where the rest of the platform assumes it does; in the author’s framing, &x no longer equals &x, and data moves out from under the pointer that names it.

That matters because every isolation mechanism the platform relies on — page tables, SMEP/SMAP, protection keys, the IOMMU, nested/EPT paging, the Platform Security Processor, and System Management Mode — enforces its guarantees on physical addresses, all of which sit above the memory controller. None of them observe the remapping that happens below. Scramble the DRAM coordinates and those fences never fire, exposing carveouts invisible even to the kernel: the PSP, SMM, C6 DRAM, and CPU microcode. The actual trigger is a single bit-flip via an xor to an MMIO register. The hard engineering is survival — keeping the machine alive while all of RAM is rearranged, which is done by disabling the other cores and interrupts, priming TLBs and warming caches, running a tight sequence entirely from cache to grab the protected data, then restoring the mapping without a trace.

The technique was developed on AMD Family 16h, the last generation whose datasheets both document these translation registers and confirm they cannot be locked; Zen (Family 17h) and later simply omit the details. The author argues the same class of transforms plausibly extends across x86, ARM, and RISC-V. The remaining obstacle is practical rather than conceptual: since the datasheets underspecify the scrambled behavior, reverse-engineering exactly what the rewired mapping produces is the real work. The broader lesson is that security primitives built on layers of address abstraction are only as trustworthy as the silicon translating addresses beneath them.