IBM claims first sub-1nm chip, packing 100B transistors with 3D 'nanostack'

IBM has announced what it calls the world’s first sub-1 nanometer chip technology, built around a new transistor architecture at the 0.7nm (7 angstrom) node. The company says it fit roughly 100 billion transistors onto a fingernail-sized die — about double the density of its 2021-era 2nm chip — and projects up to 50 percent more performance or 70 percent better energy efficiency versus that earlier node. The pitch is that meaningful scaling gains are still achievable even as feature sizes shrink toward the dimensions of individual atoms.

The core innovation is an architecture IBM calls ‘nanostack,’ described as the first three-dimensional, nanosheet-based transistor design. Rather than only shrinking transistors, it vertically stacks and staggers them using 3D sequential integration, and lets each stacked layer use different material combinations so individual transistors can be tuned separately for speed or power. IBM says it validated the approach experimentally — including dielectric bonding in CMOS integration and a working CMOS inverter — and reported 40 percent SRAM scaling in research presented at VLSI 2026, which matters for feeding bandwidth-hungry AI workloads.

The work is positioned as fuel for generative AI and cloud infrastructure, and IBM frames it as the start of an ‘angstrom era’ with at least a decade of scaling left on its roadmap. The research runs at IBM’s Albany, NY facility, which is slated to receive an ASML High-NA EUV lithography tool, with partners including Lam Research, Tokyo Electron, and SCREEN. Notably, this is a research milestone, not a shipping product: IBM only sees a path to production within roughly the next five years.