CPython adds official RISC-V support at tier 3, eyeing tier 2 next

CPython has formally recognized RISC-V as a tier 3 platform under PEP 11, marking the open instruction set architecture as an officially supported target for Python’s reference implementation. Unlike proprietary ISAs such as x86 and ARM, RISC-V is a royalty-free open standard that anyone can implement, and its ecosystem is projected to quadruple by 2032 — making reliable Python support increasingly relevant as the hardware spreads.

The milestone came out of sustained community effort rather than a single push: contributors tested on physical hardware, fixed architecture-specific bugs, and improved the build system over time. Continuous testing was a linchpin, with the RISE Project donating RISC-V machines to run CPython buildbots. Tier 3 is the lowest support level, meaning failures don’t block releases, but it establishes RISC-V as a recognized platform with dedicated maintainers.

Next steps focus on tightening the feedback loop by wiring RISC-V directly into CPython’s CI — currently buildbots only run after patches merge — with a longer-term goal of promoting the architecture to tier 2 and pursuing RISC-V-specific performance optimizations. The maintainers are asking anyone with RISC-V hardware to build CPython, run real workloads, and report breakage, and note that broader Python ecosystem support will depend on parallel work across packages, compilers, and tooling.