CPU Compiled Into Qwen Model Weights Executes RISC-V Code

Qwenputer embeds a fully functional 32-bit RISC-V CPU directly into a Qwen 3.5 4B model’s weights, requiring no external tools or runtimes. The architecture leverages Gated DeltaNet attention layers as addressable RAM by configuring them to preserve state exactly, enabling the model to execute arithmetic operations, C, and MicroPython code within its token generation process. The RISC-V core supports RV32IM, the Zba extension, and bignum operations, occupying 11 of the model’s 32 layers, and has run 18 million instructions without error.

On arithmetic tasks, the system scores 97.5% on division operations and 100% on combined multiplication-division operations. The embedded CPU also manages a persistent filesystem supporting up to 512 files, with storage capacity of approximately 53,000 tokens spread across 1,024 directory slots. Between conversations, this filesystem achieves 90% accuracy when retrieving facts that changed, compared to 30% when concatenating previous conversations.