Asahi Linux Cracks Apple Silicon Power Management Without EL3 Firmware

The latest Asahi Linux progress report centers on a stubborn obstacle to good battery life on Apple Silicon: getting CPU idle states to work within Linux’s upstreaming rules. The arm64 maintainers require all upstream hardware to manage CPU power through the standard PSCI interface, which calls into firmware via SMC or HVC instructions that yield to a higher exception level. Apple’s cores never implement EL3, so with Linux already running at EL2 there is no firmware layer to hand off to — leaving Asahi stuck on a downstream, non-upstreamable cpuidle driver. Their fix reframes m1n1, the project’s bootloader, as de facto firmware: Sven is building a PSCI conduit that routes through UEFI Runtime Services, letting the kernel call back into a resident m1n1 PSCI implementation at the same exception level. The kernel patches are already posted as an RFC.

A parallel problem forced the issue on newer chips. ARM expects cores in a WFI wait loop to retain state, but that behavior is configurable via chicken bits on M1–M3 and, starting with M4, locked down by Apple’s boot firmware. On M4 that default causes a core to lose state and crash during early boot, before the cpuidle driver loads. Yurkea’s workaround, now in linux-next, adds a kernel command-line parameter to control how cores are parked in idle — including a plain no-op loop — until the real driver can take over and save state properly.

The report closes with a look at Apple’s evolving kernel-hardening stack. The Page Protection Layer, which used hardware features to isolate page-table management from the rest of XNU, was eventually defeated by attackers and has since given way to the Secure Page Table Monitor. SPTM moves that protection into Apple’s Guarded Execution Framework — a set of exception levels running parallel to EL1/EL2 — backed by a custom SPRR page-table protection scheme, mirroring the isolation approach Apple already used to wall off components like IOMobileFramebuffer behind an IOMMU.