An Open Source Ethernet Switch ASIC Heads to the Fab

A hardware hacker is claiming what they believe is the first fully open source Ethernet switch ASIC, with silicon due back from the fab in mid-November. The motivation is a gap in the open silicon movement: while open source chip efforts have proliferated, they overwhelmingly target RISC-V CPUs and SoCs, leaving networking hardware ignored despite recent FCC attention to the strategic importance of networking gear. Open source routers and switches exist at the software and PCB level, but under the hood they all still rely on closed, proprietary chips for the actual routing and forwarding.

Rather than attempt a full router — which demands a capable CPU, specialized networking blocks, and analog front ends all at once — the author scoped the project down to a switch, and specifically a real taped-out ASIC rather than an FPGA. The design is heavily shaped by the constraints of the Tiny Tapeout digital shuttle: just 24 GPIO pins rated to 50 MHz and no analog front end. To reach 100BASE-TX Ethernet anyway, the chip offloads the physical layer to an external Microchip LAN8720A PHY and talks to it over the RMII bus, spending seven pins per interface.

Die area is the other hard limit, since the author is paying out of pocket. On-chip SRAM is expensive in area, and buffering full 1.5KB (or 9KB jumbo) frames for a store-and-forward design across three ports would blow the floorplan several times over. That constraint effectively forces a cut-through architecture — lower latency, but with the tradeoff that corrupted frames can be forwarded before the frame check sequence is validated. The piece is a candid, self-deprecating walk through the engineering compromises of building networking silicon solo on a hobbyist budget.